Fruit for the schema in the need for a round, reset for all Intel measures are removed with Eve is the capacity of the cache, such as the Core 2 Quad quad core has two-level cache 12MB, single-core Itanium have 24MB L3 cache. Now that Intel and organized following the overwhelming progress cache dilution, and talk with the new cached type. 2010 annual Super Eve range powder into upcoming arts workshop circuit full month 5-7, stop, Intel will be through process two keynote speeches, first let them are reset for cache full measure to the arts of the latest research on the subject, especially at the place of the existing SRAM \”floating units\” (Floating Body Cell/FBC).
SRAM warfare eSRAM is most often use guchen of two embedded into memory, this former six transistors, larger Eve, but the rate is very fast, the system is also very low yidu, which each unit as long as a transistor warfare capacitors, small size, rate but also ease, making system is also very hard. FBC is scattered and the two foot art is good at, each unit is the only one transistor SRAM sink specially, than many, while at the same rate faster than eSRAM, system system is relatively simple.
According to taste, Intel has made the victory for 22nm process FBC storage and utilization is very open Shi making batch produced in Bulk wafers, compared to previous experience of utilization of real SOI wafer is capital on expensive.
Another in a paper, Intel lent describes as Ann is a FBC storage after the gate (back gate) when the pick of the day fly into mixed content without affecting the rest of the equipment, from component dimensions see yidu certainly includes proportionality.
In addition to Intel, Berkeley warfare Toshiba also all efforts are being made to the FBC foot arts workshop, but really now style battle Intel some differences.

Text/driving home